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data sheet no. pd60046-s typical connection product summary v offset 600v max. i o +/- 130 ma / 270 ma v out 10 - 20v t on/off (typ.) 680 & 150 ns deadtime (typ.) 520 ns half-bridge driver features ? floating channel designed for bootstrap operation fully operational to +600v tolerant to negative transient voltage dv/dt immune ? gate drive supply range from 10 to 20v ? undervoltage lockout ? 3.3v, 5v and 15v input logic compatible ? cross-conduction prevention logic ? internally set deadtime ? high side output in phase with input ? shut down input turns off both channels ? matched propagation delay for both channels ? also available lead-free description the ir2104(s) are high voltage, high speed power mosfet and igbt drivers with dependent high and low side referenced output channels. pro prietary hvic and latch immune cmos technologies enable ruggedized monolithic construction. the logic input is compatible with standard cmos or lsttl output, down to 3.3v logic. the output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. the floating channel can be used to drive an n-channel power mosfet or igbt in the high side configuration which operates from 10 to 600 volts. www.irf.com 1 ir2104 ( s ) & (pbf) v cc v b v s ho lo com in sd sd in up to 600v to load v cc (refer to lead assignment for correct pin configuration) this/these diagram(s) show electrical connections only. please refer to our application notes and designtips for proper circuit board layout. packages 8 lead pdip ir2104 8 lead soic ir2104s
2 ir2104 ( s ) & (pbf) www.irf.com symbol definition min. max. units v b high side floating absolute voltage -0.3 625 v s high side floating supply offset voltage v b - 25 v b + 0.3 v ho high side floating output voltage v s - 0.3 v b + 0.3 v cc low side and logic fixed supply voltage -0.3 25 v lo low side output voltage -0.3 v cc + 0.3 v in logic input voltage (in & sd ) -0.3 v cc + 0.3 dv s /dt allowable offset supply voltage transient ? 50 v/ns p d package power dissipation @ t a +25 c (8 lead pdip) ? 1.0 (8 lead soi c) ? 0.625 rth ja thermal resistance, junction to ambient (8 l ead pdip) ? 125 (8 lead soic) ? 200 t j junction temperature ? 150 t s storage temperature -55 150 t l lead temperature (soldering, 10 seconds) ? 300 absolute maximum ratings absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. all voltage parameters are absolute voltages referenced to com. the thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. symbol definition min. max. units v b high side floating supply absolute voltage v s + 10 v s + 20 v s high side floating supply offset voltage note 1 600 v ho high side floating output voltage v s v b v cc low side and logic fixed supply voltage 10 20 v lo low side output voltage 0 v cc v in logic input voltage (in & sd )0v cc t a ambient temperature -40 125 note 1: logic operational for v s of -5 to +600v. logic state held for v s of -5v to -v bs . (please refer to the design tip dt97-3 for more details). recommended operating conditions the input/output logic timing diagram is shown in figure 1. for proper operation the device should be used within the recommended conditions. the v s offset rating is tested with all supplies biased at 15v differential. c v v w c/w c
3 ir2104 ( s ) & (pbf) www.irf.com symbol definition min. typ. max. units test conditions v ih logic ?1? (ho) & logic ?0? (lo) input voltage 3 ? ? v cc = 10v to 20v v il logic ?0? (ho) & logic ?1? (lo) input voltage ? ? 0.8 v cc = 10v to 20v v sd,th+ sd input positive going threshold 3 ? ? v cc = 10v to 20v v sd,th- sd input negative going threshold ? ? 0.8 v cc = 10v to 20v v oh high level output voltage, v bias - v o ? ? 100 i o = 0a v ol low level output voltage, v o ? ? 100 i o = 0a i lk offset supply leakage current ? ? 50 v b = v s = 600v i qbs quiescent v bs supply current ? 30 55 v in = 0v or 5v i qcc quiescent v cc supply current ? 150 270 v in = 0v or 5v i in+ logic ?1? input bias current ? 3 10 v in = 5v i in- logic ?0? input bias current ? ? 1 v in = 0v v ccuv+ v cc supply undervoltage positive going 8 8.9 9.8 threshold v ccuv- v cc supply undervoltage negative going 7.4 8.2 9 threshold i o+ output high short circuit pulsed current 130 210 ? v o = 0v pw 10 s i o- output low short circuit pulsed current 270 360 ? v o = 15v pw 10 s symbol definition min. typ. max. units test conditions t on turn-on propagation delay ? 680 820 v s = 0v t off turn-off propagation delay ? 150 220 v s = 600v t sd shutdown propagation delay ? 160 220 t r turn-on rise time ? 100 170 t f turn-off fall time ? 50 90 dt deadtime, ls turn-off to hs turn-on & 400 520 650 hs turn-on to ls turn-off static electrical characteristics v bias (v cc , v bs ) = 15v and t a = 25 c unless otherwise specified. the v in , v th and i in parameters are referenced to com. the v o and i o parameters are referenced to com and are applicable to the respective output leads: ho or lo. dynamic electrical characteristics v bias (v cc , v bs ) = 15v, c l = 1000 pf and t a = 25 c unless otherwise specified. v mv v ma mt delay matching, hs & ls turn-on/off ? ? 60 ns a
4 ir2104 ( s ) & (pbf) www.irf.com functional block diagram lead definitions symbol description in logic input for high and low side gate driver outputs (ho and lo), in phase with ho logic input for shutdown v b high side floating supply ho high side gate drive output v s high side floating supply return v cc low side and logic fixed supply lo low side gate drive output com low side return sd lead assignments 8 lead pdip 8 lead soic ir2104 ir2104s 1 2 3 4 8 7 6 5 v cc in sd com v b ho v s lo 1 2 3 4 8 7 6 5 v cc in sd com v b ho v s lo vb ho vs in sd dead time & shoot-through prevention pulse gen pulse filter hv level shift r s q vcc lo com uv detect
5 ir2104 ( s ) & (pbf) www.irf.com figure 5. delay matching waveform definitions ho 50% 50% 10% lo 90% mt ho lo mt in (lo) in (ho) figure 4. deadtime waveform definitions in ho 50% 50% 90% 10% lo 90% 10% dt dt figure 3. shutdown waveform definitions sd t sd ho lo 50% 90% figure 1. input/output timing diagram sd in ho lo figure 2. switching time waveform definitions in (ho) t r t on t f t off lo ho 50% 50% 90% 90% 10% 10% in (lo)
6 ir2104 ( s ) & (pbf) www.irf.com figure 6a. turn-on time vs temperature figure 6b. turn-on time vs supply voltage figure 7a. turn-off time vs temperature figure 7b. turn-off time vs supply voltage temperature (c) vbias supply voltage (v) temperature (c) vbias supply voltage (v) turn-off delay time (ns) 0 100 200 300 400 500 10 12 14 16 18 20 ma x . ty p. turn-off delay time (ns) 0 200 400 600 800 1000 1200 1400 -50 -25 0 25 50 75 100 125 t u rn -o n d e l ay ti me (ns) max. typ. turn-on delay time (ns) 0 200 400 600 800 1000 1200 1400 10 12 14 16 18 20 max . ty p. 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 max. typ. 0 200 400 600 800 1000 0 2 4 6 8 101214161820 turn-on delay time (ns ) max . typ . 0 200 400 600 800 1000 0 2 4 6 8 101214161820 turn-off delay time (ns max . typ figure 7c. turn-off time vs input voltage figure 6c. turn-on time vs input voltage input voltage (v) input voltage (v)
7 ir2104 ( s ) & (pbf) www.irf.com figure 8a. shutdown time vs temperature figure 8b. shutdown time vs voltage vbias supply voltage (v) temperature (c) shutdown delay time (ns) 0 100 200 300 400 500 10 12 14 16 18 20 max . ty p. shutdown delay time (ns) 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 typ. m ax. figure 10a. turn-off fall time vs temperature temperature (c) vbias supply voltage (v) figure 10b. turn-off fall time vs voltage turn-off fall time (ns) 0 50 100 150 200 10 12 14 16 18 20 m ax. typ. turn-off fall time (ns) figure 9a. turn-on rise time vs temperature figure 9b. turn-on rise time vs voltage temperature (c) vbias supply voltage (v) 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 max . typ. turn-on rise time (ns) 0 100 200 300 400 500 10 12 14 16 18 20 max. typ. turn-on rise time (ns) 0 50 100 150 200 -50-25 0 25 50 75100125 max . typ.
8 ir2104 ( s ) & (pbf) www.irf.com temperature (c) figure 12a. logic "1" (ho) & logic ?0? (lo) & inactive sd input voltage vs temperature figure 12b. logic "1" (ho) & logic ?0? (lo) & inactive sd input voltage vs voltage figure 13a. logic "0" (ho) & logic ?1? (lo) & active sd input voltage vs temperature temperature (c) vcc supply voltage (v) figure 13b. logic "0" (ho) & logic ?1? (lo) & active sd input voltage vs voltage vcc supply voltage (v) 0 1 2 3 4 5 6 7 8 -50 -25 0 25 50 75 100 125 i nput v ol ta g e ( v ) mi n. 0 0.8 1.6 2.4 3.2 4 10 12 14 16 18 20 i nput v ol tage (v ) max . 0 1 2 3 4 5 6 7 8 10 12 14 16 18 20 i nput v ol tage (v ) mi n. 0 0.8 1.6 2.4 3.2 4 -50-250 255075100125 input voltage (v) ma x . temperature (c) vbias supply voltage (v) deadtime (ns) figure 11a. deadtime vs temperature deadtime (ns) figure 11b. deadtime vs voltage 0 200 400 600 800 1000 1200 1400 -50 -25 0 25 50 75 100 125 max. typ. mi n. 0 200 400 600 800 1000 1200 1400 10 12 14 16 18 20 m ax. typ. mi n.
9 ir2104 ( s ) & (pbf) www.irf.com temperature (c) vcc supply voltage (v) figure 14a. high level output vs temperature figure 14b. high level output vs voltage 0 0.2 0.4 0.6 0.8 1 10 12 14 16 18 20 m ax. high level output voltage (v) 0 0.2 0.4 0.6 0.8 1 -50 -25 0 25 50 75 100 125 max. high level output voltage (v) figure 15a. low level output vs temperature temperature (c) vcc supply voltage (v) figure 15b. low level output vs voltage offset supply leakage current ( a) temperature (c) figure 16a. offset supply current vs temperature low level output voltage (v) 0 0.2 0.4 0.6 0.8 1 10 12 14 16 18 20 m ax. offset supply leakage current ( a) figure 16b. offset supply current vs voltage 0 0.2 0.4 0.6 0.8 1 -50-250 255075100125 max. low level output voltage (v) 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 max. 0 100 200 300 400 500 0 100 200 300 400 500 600 max . vb boost voltage (v)
10 ir2104 ( s ) & (pbf) www.irf.com figure 18a. vcc supply current vs temperature vcc supply current ( a) vcc supply current ( a) figure 18b. vcc supply current vs voltage vcc supply voltage (v) figure 19a. logic"1" input current vs temperature temperature (c) logic 1? input current ( a) logic 1? input current ( a) figure 19b. logic"1" input current vs voltage 0 100 200 300 400 500 600 700 10 12 14 16 18 20 max. typ. 0 5 10 15 20 25 30 -50 -25 0 25 50 75 100 125 max. typ. 0 5 10 15 20 25 30 10 12 14 16 18 20 max. typ. vcc supply voltage (v) 0 100 200 300 400 500 600 700 -50-250 255075100125 max. typ. temperature (c) figure 17a. v bs supply current vs temperature figure 17b. v bs supply current vs voltage vbs floating supply voltage (v) temperature (c) vbs supply current ( a) vbs supply current ( a) 0 30 60 90 120 150 10 12 14 16 18 20 max . ty p. 0 30 60 90 120 150 -50 -25 0 25 50 75 100 125 max. typ.
11 ir2104 ( s ) & (pbf) www.irf.com logic ?0? input current ( a) figure 20a. logic "0" input current vs temperature temperature (c) vcc supply voltage (v) figure 20b. logic "0" input current vs voltage 0 1 2 3 4 5 10 12 14 16 18 20 logic "0" input current (ua) max . 0 1 2 3 4 5 -50 -25 0 25 50 75 100 125 ma x . vcc uvlo threshold +(v) figure 21a. vcc undervoltage threshold(+) vs temperature temperature (c) figure 21b. vcc undervoltage threshold(-) vs temperature vcc uvlo threshold - (v) output source current (ma) figure 22a. output source current vs temperature temperature (c) figure 22b. output source current vs voltage output source current (ma) 6 7 8 9 10 11 -50 -25 0 25 50 75 100 125 max . min. ty p. 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 typ. min . 6 7 8 9 10 11 -50 -25 0 25 50 75 100 125 max. mi n. typ. temperature (c) 0 100 200 300 400 500 10 12 14 16 18 20 typ. mi n. vbias supply voltage (v)
12 ir2104 ( s ) & (pbf) www.irf.com output sink current (ma) temperature (c) figure 23a. output sink current vs temperature figure 23b. output sink current vs voltage output sink current (ma) 0 100 200 300 400 500 600 700 -50 -25 0 25 50 75 100 125 typ. mi n. 0 100 200 300 400 500 600 700 10 12 14 16 18 20 typ. mi n. vbias supply voltage (v) case outlines 01-6014 01-3003 01 (ms-001ab) 8 lead pdip
13 ir2104 ( s ) & (pbf) www.irf.com 01-6027 01-0021 11 (ms-012aa) 8 lead soic 87 5 65 d b e a e 6x h 0.25 [.010] a 6 4 3 12 4. outline conforms to jedec outline ms-012aa. notes: 1. dimensioning & toleranc ing per asme y14.5m-1994. 2. controlling dimension: millimeter 3. dimensions are shown in millimeters [inches]. 7 k x 45 8x l 8x c y footprint 8x 0.72 [.028] 6.46 [.255] 3x 1.27 [.050] 8x 1.78 [.070] 5 dimension does not include mold protrusions. 6 dimension does not include mold protrusions. mold protrusions no t to exc eed 0.25 [.010]. 7 dimension is the length of lead for soldering to a substrate. mold protrusions no t to exc eed 0.15 [.006]. 0.25 [.010] cab e1 a a1 8x b c 0.10 [.004] e1 d e y b a a1 h k l .189 .1497 0 .013 .050 basic .0532 .0040 .2284 .0099 .016 .1968 .1574 8 .020 .0688 .0098 .2440 .0196 .050 4.80 3.80 0.33 1.35 0.10 5.80 0.25 0.40 0 1.27 basic 5.00 4.00 0.51 1.75 0.25 6.20 0.50 1.27 min max millimeters in c h e s min max dim 8 e c .0075 .0098 0.19 0.25 .025 basic 0.635 basic
14 ir2104 ( s ) & (pbf) www.irf.com leadfree part marking information order information lead free released non-lead free released part number date code irxxxxxx yww? ?xxxx pin 1 identifier ir logo lot code (prod mode - 4 digit spn code) assembly site code per scop 200-002 p ? marking code basic part (non-lead free) 8-lead pdip ir2104 order ir2104 8-lead soic ir2104s order ir2104s leadfree part 8-lead pdip ir2104 order ir2104pbf 8-lead soic ir2104s order ir2104spbf ir world headquarters: 233 kansas st., el segundo, california 90245 tel: (310) 252-7105 this product has been qualified per industrial level data and specifications subject to change without notice. 4/2/2004
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